Analog/digital conversion devices which have been proposed include pipeline analog/digital converters (see Patent Document 1, for example), algorithmic analog/digital converters (e.g. Patent Document 2) and cyclic analog/digital conversion circuits (e.g. Patent Document 3).
Among these devices, algorithmic analog/digital converters and cyclic analog/digital conversion circuits can be made relatively small in size and are therefore suitable for reducing an integrated circuit (IC) area.
FIG. 13 shows block diagrams related to an example of a conventional analog/digital converter (ADC).
An analog/digital conversion device 1 illustrated in FIG. 13 is an algorithmic ADC, and includes sample-and-hold circuits 11 and 12, a one-bit A/D conversion circuit 13, a subtraction circuit 14, a one-bit D/A conversion circuit 15, an amplifier circuit 16, and switches SW11, SW12, SW21 and SW22.
Next is described the operation of the algorithmic ADC.
First, as illustrated in FIG. 13(A), the switch SW10 is turned ON while the switches SW11, SW12, SW21 and SW22 are turned OFF, and the sample-and-hold circuit 11 samples an input signal.
Next, as illustrated in FIG. 13(B), the switch SW10 is turned OFF, the switches SW11 and SW12 are turned ON, and the switches SW21 and SW22 remain OFF. Accordingly, the input signal held by the sample-and-hold circuit 11 is supplied to the one-bit A/D conversion circuit 13. The one-bit A/D conversion circuit 13 converts the signal sampled and held by the sample-and-hold circuit 11 into a one-bit digital value. In this way, the most significant bit of a digital value for the conversion can be obtained.
Also, at this point, the signal sampled and held by the sample-and-hold circuit 11 is supplied to the subtraction circuit 14, at which a reference voltage Vref supplied from the one-bit D/A conversion circuit 15 in accordance with the one-bit digital value of the one-bit A/D conversion circuit 13 is subtracted from the sampled and held signal.
The one-bit D/A conversion circuit 15 supplies the reference voltage Vref to the subtraction circuit 14 in the case where the one-bit digital value of the one-bit A/D conversion circuit 13 is “1” and outputs no voltage (0 V) to the subtraction circuit 14 in the case where the one-bit digital value of the one-bit A/D conversion circuit 13 is “0”.
In the case where the one-bit digital value of the one-bit A/D conversion circuit 13 is “1”, the subtraction circuit 14 obtains a voltage by subtracting the reference voltage Vref from the sampled-and-held signal and supplies the obtained voltage to the amplifier circuit 16. In the case where the one-bit digital value of the one-bit A/D conversion circuit 13 is “0”, the subtraction circuit 14 supplies to the amplifier circuit 16 the signal sampled and held by the sample-and-hold circuit 11 without change.
The amplifier circuit 16 amplifies twice the output of the subtraction circuit 14. At this point, since the switch SW12 is ON and the switch SW22 is OFF as shown in FIG. 13(B), the signal amplified by the amplifier circuit 16 is sampled and held by the sample-and-hold circuit 12.
When the signal amplified by the amplifier circuit 16 is sampled and held by the sample-and-hold circuit 12, the switches SW21 and SW22 are turned ON while the switches SW11 and SW12 are turned OFF, as illustrated in FIG. 13(C). Accordingly, the signal sampled and held by the sample-and-hold circuit 12 is subjected to a one-bit AD conversion. In addition, a second high order bit of the digital value for the conversion can be obtained.
The operational steps, as depicted in FIGS. 13(B) and 13(C), are repeated a number of times equal to the number of bits of the output digital data, whereby the input analog signal can be converted into digital data.
Thus, the algorithmic ADC converts an input analog signal into digital data by processing the aforementioned signal in a cyclic manner. In this manner, the algorithmic ADC is able to perform conversion operations with a minimum necessary circuit size using such a cyclic process, and the circuit size can, therefore, be reduced.    [Patent Document 1] Japanese Patent Publication No. 3765797    [Patent Document 2] Japanese Patent Publication No. 3046005    [Patent Document 3] Japanese Laid-open Patent Application Publication No. 2004-357279